Key points
- China's IMECAS built gate-all-around transistors without EUV
- Immersion DUV, aimed at future 3nm chips
- Key dimensions undisclosed, no timetable given
- A test of ASML's EUV chokepoint, not yet a breach
China's Institute of Microelectronics says it has built working gate-all-around transistors as part of research targeting a future 3nm-class process, without using the extreme ultraviolet, or EUV, machines China is barred from buying. The result is an early lab demonstration, not a manufacturing process. IMECAS gave no timetable for a commercial Chinese 3nm node.
The institute, part of the Chinese Academy of Sciences and known as IMECAS, made stacked-nanosheet gate-all-around transistors using immersion DUV lithography. DUV is the optical lithography technology fabs use when they cannot rely on EUV. Ye Tianchun, a chief engineer on China's national chip program, told the IC World conference in Beijing that the team had completed what he called "early process integration." Tom's Hardware reported the work on Sunday, citing DigiTimes' account of his speech.
What the numbers show, and what they do not
IMECAS reported on/off current ratios of 970,000 and 760,000. Those results indicate that the gate was controlling the stacked channels. But the institute did not disclose the dimensions needed to compare the devices with a commercial 3nm process.
Gate-all-around is a transistor design in which the gate surrounds the channel. It improves control as components shrink, which is why leading-edge manufacturers have moved beyond the older FinFET design.
IMECAS disclosed no gate pitch, metal pitch, nanosheet size or transistor density. Those measures would be needed to compare the devices with 3nm-class chips made by Intel (INTC), Samsung and TSMC (TSM). Tom's Hardware described the result as validation of a DUV-based process flow, rather than evidence of a complete 3nm process, and noted that no research paper accompanied the claim.
Why the EUV constraint matters
ASML (ASML) is the only company that makes EUV scanners, one of the hardest chokepoints in the AI chip supply chain. Export controls have prevented Chinese fabs from buying the machines.
SMIC has produced 7nm-class chips with DUV multipatterning, a method that repeats patterning steps instead of using EUV. Applying that approach to gate-all-around devices would add process complexity and make high-volume manufacturing harder. IMECAS has not shown that it can do so at commercial yield.
A working transistor is one component of a manufacturable chip process. A commercial node also requires repeatable lithography, etch, deposition, interconnect and yield across a full wafer. The institute has not disclosed that broader process.
